RETROSPECTIVE: Scale-Out Processors - Lotfi-Kamran, Pejman; Grot, Boris; Ferdman, Michael; Volos, Stavros; Kocberber, Onur; Picorel, Javier; Jevdjic, Djordje; Adileh, Almutaz; Idgunji, Sachin; Ozer, Emre; Falsafi, Babak (ISCA@50 25-Year Retrospective: 1996-2020, 2023)
In 2012, datacenters were growing at phenomenal speed, with forecasts of unprecedented levels of electricity consumption and emissions reaching that of the airline industry. These forecasts were exacerbated by the slowdown in Dennard Scaling and extraordinary projections for chip power density. Unfortunately, datacenters were built with volume servers that inherited the basic hardware and OS organization of the 90s’ desktop PCs, with server cost (and not silicon efficiency) as the key design criterion. Many had established that there is a fundamental mismatch between desktop CPU microarchitecture and the silicon requirements of scale-out datacenter services. At that time, novel server platforms emerged with energy-efficient ARM (e.g., Calxeda, Marvell, SeaMicro) and MIPS (e.g., Tilera) cores. Because memory played a pivotal role in the cost and the basic organization of emerging scale-out services in datacenters, 32-bit ARM cores were ill-suited in the server setting and never found traction. Similarly, manycore tiled CPUs were mostly optimized for on-chip communication in parallel workloads rather than supporting server software stacks that primarily benefited from request-level parallelism and exhibited little communication across threads. The Scale-Out Processors was the product of an EU-funded project, EuroCloud Server, among ARM, EPFL, IMEC, Nokia, and University of Cyprus, to design cloud-native servers with 64-bit out-of-order ARM cores (derived from Cortex A-15) and 3D-stacked DRAM running cloud services.