EVX: Vector Execution on Low Power EDGE Cores - Duric, Milovan; Palomar, Oscar; Smith, Aaron; Unsal, Osman; Cristal, Adrian; Valero, Mateo; Burger, Doug (Proceedings of the conference on Design, Automation & Test in Europe (DATE), 2014)
In this paper, we present a vector execution model that provides the advantages of vector processors on low power, general purpose cores, with limited additional hardware. While accelerating data-level parallel (DLP) workloads, the vector model increases the efficiency and hardware resources utilization. We use a modest dual issue core based on an Explicit Data Graph Execution (EDGE) architecture to implement our approach, called EVX. Unlike most DLP accelerators which utilize additional hardware and increase the complexity of low power processors, EVX leverages the available resources of EDGE cores, and with minimal costs allows for specialization of the resources. EVX adds a control logic that increases the core area by 2.1%. We show that EVX yields an average speedup of 3x compared to a scalar baseline and outperforms multimedia SIMD extensions.