Configuration Caching and Swapping - Sudhir, Suraj; Nath, Suman; Goldstein, Seth Copen (FPL '01: Proceedings of the 11th International Conference on Field-Programmable Logic and Applications, 2001)
Speedups of coupled processor-FPGA systems over traditional microprocessor systems are limited by the cost of hardware reconﬁguration. In this paper we compare several new conﬁguration caching algorithms that reduce the latency of reconﬁguration. We also present a cache replacement strategy for a 3-level hierarchy. Using the techniques we present, total latency for loading the conﬁgurations is reduced, lowering the conﬁgurable overhead.