A Processor for a High-Performance Personal Computer - Lampson, Butler; Pier, Kenneth A. (7th IEEE Symposium on Computer Architecture, 1980)
A description is given of the design goals, microarchitecture, and implementation of the microprogrammed processor for a compact high performance personal computer. This computer supports a range of high level language environments and high bandwidth I/O devices. Besides the processor, it has a cache, a memory map, main storage, and an instruction fetch unit; these are described in other papers. The processor can be shared among 16 microcoded tasks. The machine has a 50 ns microcycle, and can execute a simple macroinstruction in one cycle; the available I/O bandwidth is 640 Mbits/sec. The entire machine, including disk, display and network interfaces, is implemented with approximately 3000 MSI components, mostly ECL 10K; the processor is about 35% of this. In addition there are up to 4 storage modules, each with about 300 16K or 64K RAMs and 200 MSI components, for a total of 8 Mbytes. Several prototypes are currently running.
Reprinted in 25 years of the International Symposia on Computer Architecture (selected papers), 1998, pp 180-194 (ISBN 978-1-58113-058-4). Also in Technical Report CSL-81-1, Xerox Palo Alto Research Center (related file).