A 0.6–107 µW Energy-Scalable Processor for Directly Analyzing Compressively-Sensed EEG - Zarar, Shuayb; Lee, Kyong Ho; Jha, Niraj K; Verma, Naveen (IEEE Trans. Circuits and Systems (TCAS) - I: Regular Papers, 2014)
Compressive sensing has been used to overcome communication constraints (energy and bandwidth) in low-power sensors. In this work, we present a seizure-detection processor that directly uses compressively-sensed electroencephalograms (EEGs) for embedded signal analysis. In addition to addressing communication, this has two advantages for local computation. First, with compressive sensing, reconstruction costs are typically severe, precluding embedded analysis; directly analyzing the compressed signals circumvents reconstruction costs, enabling embedded analysis within applications. Second, compared to Nyquist-sampled signals, the use of compressed representations reduces the computational energy of signal analysis due to the reduced number of signal samples. We describe an algorithmic formulation as well as a hardware architecture that enables two strong power-management knobs, wherein application-level performance can scale with computational energy. The two knobs are parameterized as follows: 1) ξ, which quantifies the amount of data compression, and 2) ν, which determines the approximation error within the proposed compressed-domain processing algorithm. For ξ and ν in the range 2-24×, the energy to extract signal features (over 18 channels) is 70.8-1.3 nJ, and the detector’s performance for sensitivity, latency, and specificity is 96-91%, 4.7-5.3 sec., and 0.17-0.30 false-alarms/hr., respectively (compared to a baseline performance of 96%, 4.6 sec., and 0.15 false-alarms/hr).